1. Field of the Invention
The present invention relates to technologies of a semiconductor device, a testing method and a manufacturing method thereof, etc. and, more particularly, to a semiconductor device technology suitable for testing a high-speed memory interface which the semiconductor device has. Also, the present invention relates to technologies for a method of testing an electric characteristic of a memory interface included in a semiconductor device and a method of manufacturing a semiconductor device with a memory interface.
2. Description of the Related Art
Semiconductor memories widely used in personal computers or various electric appliances are Synchronous Dynamic Random Access Memories (hereinafter referred to as “SDRAMs”). The SDRAM includes a Single Data Rate SDRAM (hereinafter referred to as “SDR-SDRAM”) and a Double Data Rate SDRAM (hereinafter referred to as “DDR-SDRAM”), and the high-speed DDR-SDRAM has been widely used. For data exchange with such a DDR-SDRAM, a semiconductor device (semiconductor integrated circuit) has recently incorporated therein a high-speed memory interface (circuit unit).
Operations of a semiconductor device including a memory interface and a semiconductor memory will be briefly described below by using FIGS. 5 to 7, in an exemplary case where the DDR-SDRAM is used as the semiconductor memory.
FIG. 5 depicts a general outline of a connection between a DDR-SDRAM 50 as a semiconductor memory and a semiconductor device 40 with a memory interface supporting that semiconductor memory. Note that unless otherwise specified, the “semiconductor device” means a semiconductor device with a memory interface. The semiconductor device 40 has various signal terminals as a memory interface, such terminals including an operation clock terminal 12 that outputs an operation clock (denoted as “MCLK”), a memory command terminal 13 that outputs a memory command, a data terminal 14 that inputs and outputs data (denoted as “DQ”), and a data strobe terminal 15 that inputs and outputs data strobe (denoted as “DQS”). In normal use, each of the terminals (12 to 15) of the memory interface of the semiconductor device 40 is connected to each corresponding terminal on a side of the DDR-SDRAM 50 via a signal line (transmission line).
MCLK is a clock signal for operation of the DDR-SDRAM 50. The memory command is a command signal for controlling the state of the DDR-SDRAM 50. The memory command comprises a plurality of signal lines and, based on the state of each of these signals (hereinafter “High-and-Low” or “described H/L”), controls the state of the DDR-SDRAM 50, such as data write (“WRITE”) and data read (“READ”). The DQ is a signal for data exchange with the DDR-SDRAM 50. The DQS is a signal for determining the DQ and a signal for notification of input/output timing.
Note that, in FIG. 5, for the purpose of simplifying the description of a connection pattern of the semiconductor device 40 with the memory interface and the DDR-SDRAM 50 for general use, a bus representation is not used for each signal and termination resistors between the semiconductor device 40 and the DDR-SDRAM 50 and others are not shown.
FIG. 6 depicts a general outline of signals (including signal input/output timing) when data is written from the semiconductor device 40 to the DDR-SDRAM 50. “T1” and the like represent time. (a) to (d) in FIG. 6 correspond to signals outputted from the relevant terminals of the semiconductor device 40.
(a) MCLK 2 represents a clock signal at a frequency corresponding to the operation speed of the DDR-SDRAM 50, and is outputted from the semiconductor device 40 to the DDR-SDRAM 50. Note that, in the present example, an inverted phase clock is omitted, and the clock signal is represented as one line. (b) memory command 3 in this case is “WRITE” 3a corresponding to a data write state setting signal. (c) DQ 4 represents a write data signal outputted from the semiconductor device 40. D1 to D4 respectively denote write data. (d) DQS 5 is outputted in accordance with DQ 4 to determine timing for establishing DQ 4 in the DDR-SDRAM 50.
From the semiconductor device 40, for example, “WRITE” 3a is outputted as (b) memory command 3 so as to establish a rising edge of MCLK 2 at a time T3 (as represented by a triangle in the drawing). The DDR-SDRAM 50 receiving “WRITE” 3a makes a transition to a data write state. When the memory interface supports the DDR-SDRAM, the semiconductor device 40 outputs (c) DQ 4 and (d) DQS 5 after outputting “WRITE” 3a (T3) and one clock after MCLK 2 (T4). The DDR-SDRAM 50 receives these DQ 4 and DQS 5, internally latches DQ 4 at timing of DQS 5 (rising and trailing), and then retains each piece of data (D1 to D4).
As for a relation between DQ 4 and DQS 5 in the DDR-SDRAM 50, a set-up time tDS and a hold time tDH are defined. This timing definition, the memory interface of the DDR-SDRAM 50, and others are standardized by Joint Electron Device Engineering Council (hereinafter referred to as “JEDEC”), which is a US industrial organization for facilitating standardization of electronic components.
FIG. 7 depicts a general outline of signals when the semiconductor device 40 reads data from the DDR-SDRAM 50 to the semiconductor device 40. As with the above, (a) MCLK 2 represents a clock signal at a frequency corresponding to the operation speed of the DDR-SDRAM 50. (b) memory command 3 in this case is “READ” 3b corresponding to a data read state setting signal. (c) DQ 4 represents a read data signal outputted from the DDR-SDRAM 50. D1 to D4 respectively denote read data. (d) DQS 5 is outputted in accordance with DQ 4 to determine timing for establishing DQ 4 in the semiconductor device 40.
From the semiconductor device 40, for example, “READ” 3b is outputted as (b) memory command 3 so as to establish a rising edge of MCLK 2 at a time T3 (as represented by a triangle in the drawing). The DDR-SDRAM 50 receiving “READ” 3b makes a transition to a data read state, that is, a retained data output state. Then, the DDR-SDRAM 50 outputs (c) DQ 4 (for example, retained data at the time of writing data) and (d) DQS 5 in synchronization with (a) MCLK 2. The semiconductor device 40 then receives these (c) DQ 4 and (d) DQS 5, and retains DQ 4 at timing of DQS 5.
When DQ 4 is read from the DDR-SDRAM 50, as for its read timing, apart from the set-up time and the hold time as described above regarding the time of data writing, there is a timing definition of “/CAS latency” (hereinafter abbreviated as “CL” and, particularly, also as “/CAS read latency”, where “/” represents a sign indicative of an inverted phase). “CAS” is an abbreviation of column address strobe. For example, in the case of DDR-SDRAM 50 of the type defined as CL=2, there is a restriction in which, DQ 4 and DQS 5 have to arrive at the semiconductor device 40 by two rising edges of MCLK 2, that is, at a time T5 after (b) “READ” 3b of the memory command 3 is outputted. In FIG. 7, for example, an example of the case of CL=2 is shown.
Also, in FIGS. 6 and 7, four consecutive pieces of data D1 to D4 are shown as DQ 4. This is defined by a burst length (hereinafter abbreviated as “BL”) of the DDR-SDRAM (50), and, by way of example, the case of being defined as BL=4 is shown. The consecutive pieces of data (DQ 4) for BL defined in the DDR-SDRAM (50) are collectively received.
There are a plurality of types of the DDR-SDRAM 50 depending on the elements including CL, BL, and further the operation speed (clock frequency of MCLK 2). The memory interface of the semiconductor device 40 is one suitable for the type of the semiconductor memory (DDR-SDRAM 50) to be connected.
Note that detailed specifications of the above-described memory (DDR-SDRAM) and memory interface and others are described in “Usage of DDR SDRAM—User's Manual”, Document No. J0234E30 (Ver. 30), issued on April, 2002, Elpida Memory, Inc., URL:    <http://www.elpida.com/ja/products/index.html>,    <http://www.elpida.com/pdf/j0234E30.pdf>.
In the test on the memory interface of the semiconductor device 40 as described above, a test on timing that complies with the specifications of the JEDEC is required due the way of usage described above. Subjects of the timing test may include the set-up time/hold time, as well as whether CL is satisfied.
In general, for electric characteristic tests on the semiconductor device, some type of semiconductor device or semiconductor test system is used. However, the memory interface of the semiconductor device has a high-speed data transfer rate such as 400 Mbps, and is therefore required to be tested by a semiconductor testing device operable at a high speed. Moreover, if the data transfer rate is 400 Mbps, for example, one data width is 2.5 ns (= 1/400 Mbps), and therefore the set-up time/hold time is 1.25 ns. Also, if it is assumed that a timing test is required to be performed with precision of one-tenth of the set-up time/hold time, a semiconductor testing device guaranteed with timing precision of 125 ps is required.
However, such a semiconductor testing device operable at a high speed and with high timing precision is extremely expensive in comparison with general semiconductor testing devices, thereby posing a problem that manufacturing costs of semiconductor devices cannot be reduced.
Japanese Patent Laid-Open Publication No. 2003-98235 discloses a technology for conducting a timing test on a memory interface by using a semiconductor testing device with an operation speed slower than the memory interface included in a semiconductor device.